Side-Channel Attacks on ARMv9-A CPUs in 2026: Extracting Crypto Keys from ARM TrustZone via Cache Timing

Executive Summary: In 2026, side-channel attacks targeting ARMv9-A CPUs have demonstrated unprecedented efficacy in extracting cryptographic keys from ARM TrustZone-protected environments. Leveraging advanced cache timing techniques, adversaries can now bypass hardware-enforced isolation with high precision, posing severe risks to secure enclaves in mobile, IoT, and cloud platforms. This report analyzes the attack surface, technical mechanisms, and mitigation strategies for securing ARM-based systems against such exploits.

Key Findings

• ARMv9-A's enhanced cryptographic extensions (e.g., ARMv8.5-A) have introduced new side-channel vulnerabilities in TrustZone.
• Cache timing attacks can now extract full AES-256 or RSA-4096 keys from TrustZone-M (embedded) and TrustZone-A (application) environments.
• Adversaries exploit speculative execution and data cache access patterns to infer secret keys with >95% accuracy in lab conditions.
• Mitigation requires a combination of software patches, microarchitectural changes, and runtime monitoring.
• Industry response includes ARM's "Pointer Authentication Code" (PAC) and "Branch Target Identification" (BTI) as partial defenses.

Technical Overview of ARMv9-A and TrustZone

ARMv9-A represents the latest iteration of ARM's high-performance architecture, incorporating hardware-level security features such as:

• TrustZone: A system-wide security framework that partitions hardware and software into "Secure" and "Normal" worlds.
• Cryptographic Extensions: Support for AES, SHA-3, and RSA in hardware, accelerating secure operations.
• Pointer Authentication: Protects against code reuse attacks by signing pointers with a cryptographic key.

TrustZone isolates sensitive operations (e.g., biometric authentication, DRM, or secure boot) in the "Secure World," while untrusted applications run in the "Normal World." Despite this isolation, side-channel attacks exploit shared microarchitectural resources—particularly the cache—to infer secrets processed in the Secure World.

Cache Timing Attacks: The Attack Vector

Cache timing attacks leverage variations in memory access latency to infer secret data. In ARMv9-A, the attack follows this sequence:

1. Prime+Probe: The attacker fills the cache with their own data, then waits for the victim (Trusted OS or app) to execute.
2. Eviction: The victim's cache accesses evict the attacker's data, leaving a trace of which cache lines were accessed.
3. Probe: The attacker measures access times to reconstruct the victim's memory access pattern.
4. Key Inference: By correlating access patterns with known cryptographic operations (e.g., AES S-box lookups), the attacker deduces the secret key.

In 2026, researchers have refined this technique using:

• Speculative Execution: Exploiting ARMv9's out-of-order pipelines to leak data before it is committed.
• Hyperthreading: On multi-core ARMv9-A CPUs, attackers use sibling threads to monitor cache state in real time.
• DMA Access: Direct Memory Access controllers in ARM SoCs (e.g., Apple M-series, Qualcomm Snapdragon) allow cache probing without CPU intervention.

Case Study: Extracting RSA Keys from TrustZone-A

A 2026 study published in USENIX Security demonstrated a sustained attack on a Qualcomm Snapdragon 8 Gen 3 (ARMv9-A) device running Android with TrustZone-A. The attack targeted the Android Keystore, which uses TrustZone to store cryptographic keys. Key steps included:

• Target Selection: The Keystore's RSA-2048 key generation and signing operations.
• Cache Profiling: A malicious app repeatedly triggered RSA signing while monitoring the L1/L2 cache via assembly instructions (e.g., DC CIVAC).
• Machine Learning: A neural network trained on cache access patterns to predict the key with 92% accuracy after 10,000 observations.
• Key Recovery: Full key extraction achieved in under 3 minutes on a device with a 3.2 GHz Cortex-X4 core.

Defense Mechanisms and Limitations

Current mitigation strategies include:

• ARM Pointer Authentication (PAC): Protects code pointers but does not fully address data cache leakage.
• Constant-Time Cryptography: Enforces uniform memory access patterns, but increases latency by ~15-20%.
• Cache Partitioning: ARMv9-A's "Cache Lookaside Buffer" (CLB) allows partitioning cache ways between Secure/Normal worlds. However, this is not enabled by default in most SoCs.
• Runtime Monitoring: Hardware Performance Counters (HPCs) can detect unusual cache activity, but are often disabled in production devices.
• Firmware Updates: ARM's 2026 Trusted Firmware-A (TF-A) includes patches for speculative execution leaks, but adoption is slow due to OEM fragmentation.

Critical Limitation: None of these defenses are universally implemented. Most consumer devices (e.g., smartphones, smart TVs) lack cache partitioning or PAC, leaving them vulnerable to side-channel attacks.

Recommendations for Stakeholders

For Hardware Vendors (ARM, Qualcomm, Apple, Samsung)

• Enable cache partitioning by default in ARMv9-A SoCs (e.g., via TrustZone Configuration Registers).
• Deprecate shared cache architectures in favor of per-core L2/L3 caches for Secure World operations.
• Integrate runtime cache monitoring into ARM CoreSight for anomaly detection.
• Provide firmware update mechanisms for OEMs to deploy side-channel mitigations within 30 days of patch release.

For Software Developers (Android, iOS, IoT)

• Adopt constant-time cryptographic libraries (e.g., BoringSSL's CT_* APIs).
• Use ARMv9-A's PAC for all pointer-based operations in TrustZone.
• Implement application-level cache flushing before and after cryptographic operations.
• Avoid speculative execution in security-critical code paths (e.g., via #pragma GCC unroll 0).

For End Users and Enterprises

• Apply firmware updates immediately upon release, prioritizing devices handling sensitive data (e.g., biometric systems, payment terminals).
• Isolate high-value workloads (e.g., HSMs, DRM) to dedicated ARMv9-A cores with disabled hyperthreading.
• Monitor for unusual performance degradation, which may indicate cache probing activity.
• Consider hardware security modules (HSMs) or FPGA-based alternatives for long-term key storage.

Future Outlook and Research Directions

As of Q2 2026, the cybersecurity community is exploring:

• AI-Based Detection: Machine learning models trained on HPC data to detect cache timing anomalies in real time.
• Hardware Randomization: Dynamically re-mapping cache lines to disrupt attacker profiling (e.g., "Cache ASLR").
• Secure Enclaves: Transitioning from TrustZone to more robust solutions like Intel TDX or AMD SEV in ARM environments (e.g., AWS Nitro Enclaves).
• Quantum-Resistant Cryptography: Post-quantum algorithms (e.g., Kyber, Dilithium) resistant to side-channel attacks due to smaller memory foot