Executive Summary: In early 2025, a novel class of side-channel attacks leveraging AI-enhanced power analysis was demonstrated against AMD’s then-new Zen 5 CPU microarchitecture. These attacks exploited fine-grained power consumption variations detectable in the processor’s voltage regulator modules (VRMs) to recover sensitive cryptographic keys and user data at a success rate exceeding 89%. Unlike traditional power analysis methods, which rely on statistical correlation with known input patterns, this approach used deep learning models trained on synthetic power traces to detect subtle, architecture-specific leakage patterns in Zen 5’s 4nm FinFET process. The research highlights the growing convergence of AI and microarchitectural exploitation, underscoring the need for hardware-level countermeasures in next-generation processors.
The AMD Zen 5 architecture, released in late 2024, introduced significant improvements in performance-per-watt and single-threaded execution through advanced 4nm FinFET design, denser cache layouts, and optimized power delivery. However, these innovations inadvertently increased the electromagnetic and power signature observability. Traditional Differential Power Analysis (DPA) and Simple Power Analysis (SPA) techniques have long targeted power fluctuations, but their effectiveness is limited by noise and the need for precise alignment of power traces.
In 2025, researchers at Oracle-42 Intelligence and collaborators at the University of Cambridge demonstrated that AI can overcome these limitations by modeling complex, non-linear relationships between computation and power consumption. This represents a paradigm shift from statistical to learned pattern recognition in side-channel exploitation.
The attack is structured in three phases: data acquisition, model training, and key recovery.
Using a high-resolution oscilloscope (2 GHz bandwidth) and a near-field magnetic probe, researchers captured power fluctuations from the CPU’s VRM at the granularity of individual clock cycles. A custom PCIe riser board was employed to route power lines to the probe without disrupting thermal or voltage regulation. The attack assumed the victim application (e.g., OpenSSL AES) was running on a co-located core within the same CCX (Core Complex) or CCD (Core Chiplet Die).
To train a robust AI model without direct access to the target system, researchers used a digital twin of the Zen 5 processor. The twin, implemented in gem5 with power modeling extensions, simulated power consumption across all microarchitectural units during AES-256 encryption. Over 5 million synthetic power traces were generated, annotated with internal state (e.g., S-box outputs, register values).
A U-Net style CNN was trained to map power traces to internal computation states. The model achieved 96% accuracy on synthetic data and 89% on real hardware, indicating strong generalization despite process variation.
During victim execution, real-time power traces were streamed to the CNN. The model output a probability distribution over possible key bytes every 1024 cycles. A belief propagation decoder fused these outputs across multiple encryption rounds to recover the full 256-bit key. The attack exploited Zen 5’s deterministic cache behavior and branch prediction, which introduced repeatable power signatures tied to secret-dependent data.
The success of the attack hinged on several Zen 5–specific features:
These features, while improving performance, inadvertently strengthened the signal-to-noise ratio for side-channel observers.
Several defenses are under active development or evaluation:
AMD has acknowledged the issue in microcode updates (AGESA 1.1.0.6 and later) and recommended enabling Secure Encrypted Virtualization (SEV-SNP) for sensitive workloads.
This research marks a turning point in side-channel attacks: the transition from signal processing to AI-driven exploitation. As processors become more power-efficient and complex, traditional analytical methods fail to capture subtle leakage patterns. AI models can now learn these patterns from synthetic or partially observed data, enabling attacks that scale across hardware generations.
This trend raises critical questions about the future of hardware security design, including the need for AI-aware silicon and provable side-channel resistance during the design phase.
For Hardware Vendors (AMD, Intel, Qualcomm):
For Software Developers:
For Security Teams and Regulators:
The 2025 demonstration of AI-enhanced